1. Field of the Invention
The present invention relates to an apparatus and a method for testing electronic devices, especially for testing one or more dies on a integrated circuit (IC) wafer.
2. Description of the Related Art
Testing IC characteristics and the reliability of ICs is indispensable to the semiconductor industry. As IC manufacturing technology advances, ICs perform better and are able to work at higher frequencies with even smaller die sizes. The technology and equipment for IC testing needs to advance correspondingly. The number and density of the probes on a testing probe card should conform with those of the I/O terminals of the ICs to be tested. All the lines and leads from the probes to the Automatic Test Equipment (ATE) that generates and processes testing signals should be able to work at higher frequencies and maintain low noise to render accurate testing results. Besides, the cost of testing is an important component of the total cost of producing ICs. Therefore it is important to reduce the cost of testing.
Testing of an IC's characteristics and its reliability is carried out after the IC die has been packaged by sending and picking up test signals via the pins extending out of the IC package. Such a process does not sort out bad dies before packaging and thus wastes time and money when bad dies are packaged. Manufacturing wafers consumes the most time in the process of manufacturing IC products. In a traditional process flow the failure rate of the ICs is only known at the last stage. It is consequently normal to produce a number of surplus wafers at the first stage of IC production in anticipation of failures because it is generally not acceptable to start replacement wafer production when the IC failure rate is known. The result is that a manufacturer will keep a larger stock of wafers on hand, which increases costs.
Multi-chip modules have become more popular as advanced packaging technology has become available. In a multi-chip module any bad chip will result in the discard of the entire module. In a traditional process, testing is not done before the chips are packaged but is applied to the packaged multi-chip module. The testing thus experiences the greater complexity of the module and achieves less reliable results. The effect is higher testing costs, longer research and development cycles and costs, and a higher risk of returned goods. If individual dies were sorted before they were packaged, testing of the packaged multi-chip module would only need to identify damage caused by the packaging process, limiting the above-mentioned drawbacks.
Wafer sort technologies which test individual dies within a completed integrated circuit wafer before packaging have been developed to address the problems associated with traditional IC testing technology. FIGS. 1a and 1b illustrate a conventional wafer sort apparatus that uses cantilever type probes. FIG. 1a shows the bottom side of a probe card 10 that includes a substrate 11 with a plurality of probes 12 mounted on the bottom side of the substrate 11. The probes 12 are arranged in a fan-shape with a first end 121 of each probe 12 extending through a resin plate 13. The resin plate 13 has an opening in its central portion and is tightly attached to the substrate 11 by adhesive. The arrangement of the probes 12 corresponds to the positions of the I/O terminals (bonding pads) 21 of the integrated circuit 20 to be tested, which is to be located under the probes 12. During testing the second ends 122 of the probes 12 are aligned to contact the I/O terminals 21. The substrate 11 has a plurality of leads 14 each having a first end 141 inserted in the resin plate 13 where the first end 141 is connected to the first end 121 of each probe 12. The second end 142 of each lead 14 extends outward and is soldered to the substrate 11. To provide connection with the testing circuits, the substrate 11 comprises a plurality of terminals (not shown in the figures) electrically linked to the leads 14 via electrical lines on the surface of and inside the substrate 11.
The illustrated probe card has several drawbacks. First, using this probe card to test a die requires that the bonding pads which act as the I/O terminals of the die be located only on the circumference of the die. Secondly, due to its structural strength requirement, the cantilever type probes 12 must be made relatively thick so that the density of the probes 12 is limited. Consequently the number of I/O terminals of the die to be tested is also limited or the die must be over-sized. Thirdly, cantilever type probe cards are disadvantageous for high frequency testing. Each probe 12 combined with lead 14 forms a 1˜3 inch-long unshielded electric wire and these electric wires are closely spaced, substantially in parallel. This results in serious electromagnetic interference (“EMI”) when high frequency test signals are applied. Moreover, the different length of these wires also causes impedance mismatches that are detrimental to high frequency access time testing.
Apart from the above-mentioned cantilever type probe cards, wafer sort apparatus of different designs have been disclosed, including the flexible membrane probe device described in “Flexible Contact Probe”, IBM Technical Disclosure Bulletin, October 1972, page 1513. The device comprises a flexible dielectric film having terminals that are suited to making electrical contact with pads on integrated circuits. The terminals are connected to the flexible wires of the test electronics. The major problem of such a device is that the dimensional stability of the membrane is not sufficient to allow contacts to be made to pads on a full wafer during a burn-in temperature cycle.